Interrupts - Part II, Interrupt on RB Change
This discussion deals with the interrupt on RB change feature. It assumes the reader is familiar with the general discussion dealing with interrupts.
The PIC16C84 and most other PICs provide a feature where the program may be configured such that an interrupt occurs when there is a change on any of a number of inputs. With the 16C84 (and 16C554/558), the interrupt is caused when there is a change on the upper nibble of Port B, i.e., RB.4::RB.7.
This might be used as a power saving technique. The processor is placed in the sleep mode and is activated only when the user changes the state of any on the four inputs. The processor then performs the defined task and goes back to sleep.
We are planning to use this feature in a 2000 event, 4 Channel event data logger. An event causes a change on any of the four inputs, waking the processor. The processor determines which of the four channels on which the event occurred. It will then fetch a 32-bit elapsed time in seconds from a Dallas DS1602. 32-bits accommodates an elapsed time of some 125 years, which is a bit much. Thus, only the lower 30 elapsed time bits will be used and the two bits associated with the channel will be inserted in the bit 31 and 30 positions. These four bytes will be saved to a Microchip 24LC65 (8K by 8) EEPROM.
The general format of configuring for the Wake Up on Change interrupt is the same as with the external or timer / counter overflow interrupts. When ready for this interrupt, bit RBIE in the INTCON register is set which specifically indentifies the type of interrrupt that will be entertained. The GIE bit is then set.
On interrupt, the program vectors to location 004H. Note that interrupts are now disabled. The processor then performs the defined task, the RBIF is then cleared and the processor then returns from the interrupt service routine using the RETFIE command. Note that interrupts are now enabled.
There is a subtlety associated with the wake-up on change. PORTB must be read. The processor then stores a copy of the high nibble. The RBIF is then set and interrupt occurs when the high nibble of PORTB differs from this copy. Thus, it is important that in the interrupt service routine that PORTB be read so as to update the copy.
The following incorrect code in the interrupt service routine caused us to do a good deal of head scratching.
BCF INTCON, RBIF
Indeed, we were clearing the interrupt flag. However, as the state of the high nibble of PORTB still differed from the old copy, the processor immediately set the RBIF flag and on RETFIE, we were immediately interrupted. In fact, the MOVF PORTB, F did us no good whatever.
The correct code was;
MOVF PORTB, W
What a difference! In performing the MOVF PORTB, W, the old copy of
the high nibble of PORTB is updated with the current state. The flag is
then cleared. Thus, interrupt will occur when the high nibble of PORTB
In the interrupt service routine, PORTB is fetched and saved in NEW. Thus, the processor now has the new value as the basis for establishing if a future change occurs. The program then ascertains the specific bit which changed, and flashes an LED at a rate depending on which bit caused the interrupt. The NEW then becomes the ORIGINAL, the RBIF is cleared and when RETFIE is executed, control passes back to the main program with interrupts enabled. It is important to note that PORTB is read, thus updating the processor's copy prior to clearing RBIF.
Note that considerable time is spent flashing the LED in the interrupt service routine. If any of the four bits on the high nibble of PORTB should change prior to clearing RBIF, RBIF will again be set by the hardware as there is a change from the latest copy. Thus, on RETFIE, interupts are again enabled and another interrupt will occur. However, this is eactly what is desired; a bit on the high nibble of PORTB changed.
I am none too certain I have been any too clear. Always read PORTB so as to update the processor's reference prior to clearing RBIF. Failure to do so may cause a false interrupt as the processor compares the current state of the high nibble of PORTB with the most recent read. That is, the same change, which is in fact no change, will cause an interrupt.
Note that in this routine, the W and STATUS registers were not saved on entry into the interrupt service routine and restored prior to exit as there was nothing of value to save. Rather, the processor simply goes to sleep and awaits the interrupt.
CONSTANT LED=0 ; PORTA pin for LED
CONSTANT CH3=7 ; CH3 corresponds to PORTB.7
LOOP1 EQU VARS+0 ; outter timing loop
BTFSS STATUS, NOT_TO ; not a watch dog timer reset
; sample PORTB before going to sleep
WAKE_UP: ; interrupt service routine
INCF N, F ; N=1
INCF N, F ; N=2
BLINK: ; N is either 0, 1, 2 or 3 corresponding to the channel